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Integrated Circuit Systems, Inc.
ICS9147-06
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
The ICS9147-06 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Two different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Glitch-free Stop clock control is provided for CPU and BUS clocks. Complete chip low current mode is achieved with the Power Down# pin. High drive BUS outputs typically provide greater than 1 V/ ns slew rate into 30 pF loads. CPU outputs typically provide better than 1V/ns slew rate into 20 pF loads while maintaining 505% duty cycle. The REF and IOAPIC clock outputs typically provide better than 0.5V/ns slew rates. Separate buffer supply pins VDDL allow for nominal 3.3V voltage or reduced voltage swing (from 2.9 to 2.5V) for CPU (1:4) and IOAPIC outputs.
Features
Generates five processor, eight bus, four 14.31818 MHz, two 48 MHz clocks for USB support and one 24 MHz clock. CPU to BUS clock skew 1 to 4ns (CPU early) Synchronous clocks skew matched to 250ps window on CPU and 500ps window on BUS. Selectable multiplying ratios Glitch free stop clock controls CPUEN and BUSEN 3.0V 3.7V supply range, 2.5V to VDD supply range for CPU (1:4) clocks and IOAPIC clock. 48-pin SSOP package
Pin Configuration
Block Diagram
48-Pin SSOP
Pentium is a trademark of Intel Corporation 9147- 06 RevA 5/29/97P
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9147-06
Functionality
PD# 1 1 1 1 1 1 0 BUSEN 1 1 1 1 1 0 X CPUEN 1 1 1 1 0 1 X FS1 0 0 1 1 X X X FS0 0 1 0 1 X X X CPU (1:4) CPUH Tristate 60 66.6 REF/2 LOW Running LOW BUS Tristate 30 33.3 REF/4 Running LOW LOW REF IOAPIC Tristate 14.31818 14.31818 REF 14.31818 14.31818 LOW 24 (MHz) Tristate 24 24 REF/4 24 24 LOW 48 (MHz) Tristate 48 48 REF/2 48 48 LOW
Pin Descriptions
PIN NUMBER PIN NAME TYPE OUT PWR IN OUT OUT IN PWR OUT IN IN OUT OUT IN OUT PWR OUT DESCRIPTION 14.318 MHz reference clock outputs. Ground. Crystal input, has internal crystal load capacitor, and feedback resistor from X2. Nominally 14.31818MHz. Crystal output, has internal crystal load capacitor BUS clock outputs, operates synchronously at CPU/2. Select pin for enabling CPU and BUS clock frequencies.* Core and Buffer output clock power supply. 48 MHz clock output Device power down input, stops outputs low and shuts off crystal oscillator and PLLs when low.* Output enable for all CPU clocks, a logic low will Stop low all CPU clocks.* 3.3 (VDD3 dependent) CPU clock output CPU clock output clocks, operates at VDDL supply voltage (with IOAPIC), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. Output enable for all BUS clock, a logic low will stop Low all Bus clocks.* IOAPIC clock output. (14.318 MHz), operates at VDDL supply voltage with CPU (1:4), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. Power supply for CPU and IOAPIC block buffers, operates at nominal 3.3V VDD or reduced voltage 2.9 to 2.5V. 24 MHz clock output 1, 2, 47 REF1, REF2, REF3 3, 10, 18, 24, 30, 32, GND 37, 43, 44 4 5 8, 9, 11, 12, 13, 14, 16, 17 26, 27 7, 15, 21, 25, 34, 48 22, 23 28 29 36 38, 39, 41, 42 6 45 40, 46 33 X1 X2 BUS (1:8) FS (0:1) VDD3 48M (1:2) PD# CPUEN CPUH CPU (1:4) BUSEN IOAPIC VDDL 24M
* Has internal pull-up to V DD3.
2
ICS9147-06
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
V DDL=VDD3=3.0 3.7 V, TA = 0 70 C unless otherwise stated
DC C haracteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current I Output Low Current I Output High Current Output Low Current Output High Current Output Low Current Output High Current Output Low Voltage I I SYMBOL V V I I
IL
TEST CONDITIONS
MIN 0.7V
DD
TYP -10.5 33.0
MAX 0.2VDD 5.0 -
UNITS V V A A mA
IH
IL
VIN=0V VIN=VDD VOL=0.8V; for CPUH, BUS & REF1 (and CPU & IOAPIC at VDDL= 3.0 to 3.7V) VOH=2.0V; for CPUH, BUS & REF1 (and CPU & IOAPIC at VDDL = 3.0 to 3.7V) VOL=0.8V; REF (2:3), 24, 48 CLKs VOH=2.0V; REF (2:3), 24, 48 CLKs VOL=0.8V; for CPUL at VDDL = 2.5V VOH = 1.7V; for CPUL at VDDL = 2.5V IOL = 10mA; for CPUH, BUS & REF1 (and CPUL at VDDL = 3.0 to 3.7V) IOH = -10mA; for CPUH, BUS & REF (and CPUL at VDDL = 3.0 to 3.7V) IOL = 8mA IOH = -8mA IOL = 8 mA; for CPUL at VDDL = 2.5V
-28.0 -5.0 -
IH
OL1
OH1
-
-28.0 26.0 -21.0 26 24 0.22
0.4
mA mA mA mA mA V
OL2
OH2 OL3
I I
OH3
V
OL1
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Supply Current Supply Current
V
OH1 OL2
2.4 2.4 2.1 -
2.8 0.25 2.6 0.25 2.25 70 230
0.4 0.4 140 500
V V V V V mA A
V V
OH2 OL3
V V
OH3 DD DD
IOH = -8mA; for CPUL at VDDL = 2.5V
@66.6 MHz; all outputs unloaded PD#
I I
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9147-06
Electrical Characteristics at 3.3V
V DDL=VDD3=3.0 3.7 V, TA = 0 70 C unless otherwise stated
AC Characteristics
PARAMETER Rise Time
1
SYMBOL Tr1 Tf1 Tr2 Tf2 Tr1 Tf1 Tr2 Tf2 Tr3 Tf3 Tr4 Tf4
Fall Time1 Rise Time1 Fall Time1 Rise Time1 Fall Time1 Rise Time1 Fall Time1 Rise Time1 Fall Time1 Rise Time1 Fall Time1 Duty Cycle Duty Cycle
1
Dt1 Dt2 Tjis1 Tjab1
1
Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma Jitter, Absolute1 Input Frequency 1 Logic Input Capacitance 1 Oscillator Input Capacitance 1 Power-on Time1 Clock Skew1 Clock Skew Clock Skew
1 1
Tjis2 Tjab2 Fi CIN CINX ton Tsk1 Tsk2 Tsk3 Tsk4 Tsk5 Tsk6
TEST CONDITIONS 20pF load, 0.8 to 2.0V CPU, BUS & REF1 20pF load, 2.0 to 0.8V CPU, BUS & REF1 20pF load, 20% to 80% CPU, BUS & REF1 20pF load, 80% to 20% CPU, BUS & REF1 30pF load, 0.8 to 2.0V CPU, BUS & REF1 30pF load, 2.0 to 0.8V CPU, BUS & REF1 30pF load, 20% to 80% CPU, BUS & REF1 30pF load, 80% to 20% CPU, BUS & REF1 20pF load, 0.8 to 2.0V 24 & 48 clocks & REF (2:3) 20pF load, 2.0 to 0.8V 24 & 48 clocks & REF (2:3) 20pF load, 0.4 to 2.0V , CPU with VDDL = 2.5V and IOAPIC 20pF load, 2.0 to 0.4V, CPU with VDDL = 2.5V and IOAPIC 20pF load @ VOUT=1.4V REF (1:3) CPU & Fixed BUS Load=20pF, BUS; Load = 30pF CPU & Fixed BUS Load=20pF, BUS; Load = 30pF REF1; Load = 47pF REF1; Load = 47pF Logic input pins X1, X2 pins From VDD=3.0V to 1st crossing of 66.6 MHz VDD supply ramp < 1 ms CPU to CPU; Load=20pF; @1.4V (Same VDD) BUS to BUS; Load=20pF; @1.4V CPU to BUS; Load=20pF; @1.4V (CPU is early) (All at 3.3V) CPU @ 2.5 to CPUH @ 3.3V CPU @ 2.5V to BUS @ 3.3V REF @ 3.3V to IOAPIC @ 2.5V
MIN 45 40 -250 -500 12.0 1
TYP 0.9 0.8 1.5 1.4 0.9 0.8 1.5 1.4 50 45 50 55 200 14.318 5 18 1.5 150 300 3.3
MAX 1.5 1.4 2.5 2.4 1.5 1.4 2.5 2.4 -
UNITS ns ns ns ns ns ns ns ns ns ns
1.6 1.6 55 50 150 250 250 500 16.0 3.0 250 500 4
ns ns % % ps ps ps ps MHz pF pF ms ps ps ns
Clock Skew1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9147-06
Recommended PCB Layout for ICS9147-06
NOTE: This PCB Layout is based on a 4 layer board with an internal Ground (common) and Vcc plane. Placement of components will depend on routing of signal trace. The 0.1uf Capacitors should be placed as close as possible to the Power pins. Placement on the backside of the board is also possible. The Ferrite Beads can be replaced with 10-15ohm Resistors. For best results, use a Fixed Voltage Regulator between the main (board) Vcc and the different Vdd planes.
5
ICS9147-06
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC MIN. .620
D NOM. .625
N MAX. .630 48
Ordering Information
ICS9147F-06
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device
6
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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