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PRELIMINARY
CUSTOMER PROCUREMENT SPECIFICATION
Z89302/04/06
DIGITAL TELEVISION CONTROLLER
FEATURES
Device Z89302 Z89304 Z89306 ROM (KB) 24 16 12 RAM* (Bytes) 640 640 640 Speed MHz 12 12 12
s s s s s s s
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0C to +70C Temperature Range Fully Customized Character Set Character-Control and Closed-Caption Modes Keypad User Control TV Tuner Serial Interface Direct Video Signals
Note: * General-Purpose
40-Pin DIP Packages 4.75- to 5.25-Volt Operating Range
s
GENERAL DESCRIPTION
The Z89302/04/06 Digital Television Controllers are designed to provide complete audio and video control of television receivers, video recorders, and advanced onscreen display facilities. The Television Controllers feature a Z89C00 RISC processor core that controls the on-board peripheral functions and registers using the standard processor instruction set. Character attributes can be controlled through two modes: the on-screen display Character-Control Mode and the Closed-Caption Mode. The Character-Control Mode provides access to the full set of attribute controls, allowing the modification of attributes on a character-by-character basis. The insertion of control characters permits direction of other character attributes. The fully customized 512 character set, formatted in two 256 character banks, can be displayed with a host of display attributes that include underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency. Serial interfacing with the television tuner is provided through the tuner serial port. Other serial devices, such as digital channel tuning adjustments, may be accessed through the industry-standard I2C port. User control can be monitored through the keypad scanning port, or the 16-bit remote control capture register. Receiver functions such as color and volume can be directly controlled by eight 8-bit pulse width modulated ports. The Z89302/04/06 has two internal 12 MHz VCOs that are referenced to a 32 kHz internal oscillator to provide the system clock. In Sleep Mode, the controller uses the 32 kHz clock for the system clock to reduce power consumption. The processor can be suspended by placing it into STOP Mode when main power is not available for low-power consumption.
CP96TEL1803 (9/96)
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Z89302/04/06 Digital Television Controller
PRELIMINARY
GENERAL DESCRIPTION (Continued)
Capture IRIN ADC Port 17 Port 00 ADC0 ADC1 ADC2 ADC3
PWM PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 Port1 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19
Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Control XTAL1 XTAL2 LPF HSYNC VSYNC /Reset CPU RAM 640 x 16
Address ROM Addr Data
Note: Dotted pin functions not available on 40-pin device.
I2C
SCL SCD
Port 01/11 Port 02/12
Register Addr/Data
OSD V1 V2 V3 BLANK HALFBLNK ROM 12K x 16 16K x 16 24K x 16
Port0F
ROM Data
Note: Z89306 has 12K words of ROM. Z89304 has 16K. Z89302 has 24K.
Figure 1. Z8930X Functional Block Diagram
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PRELIMINARY
Z89302/04/06 Digital Television Controller
PIN DESCRIPTION
PWM9 IRIN Port 18/G<0> Port 00/ADC2 Port 01/I2SSC Port 02/I2SSD Port 03 Port 04/ADC4 Port 05/ADC3 Port 06/Counter Port 07/C Sync Port 08/R<1> Port 09 Port 10/R<0> Port 11/I2MSC Port 12/I2MSD Port 13/G<1> Port 14/B<0> Port 15/B<1> Port 16/SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34
PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 CVI/ADC0 LPF XTAL2 GND XTAL1 VCC /Reset Port 17/ADC1 VBlank V1 V2 V3 VSync HSync
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Z89302 Z89304 Z89306 40-Pin DIP
33 32 31 30 29 28 27 26 25 24 23 22 21
Figure 2. 40-Pin DIP Configuration
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Z89302/04/06 Digital Television Controller
PRELIMINARY
PIN DESCRIPTIONS Z89302/03/06/07
Reset Configuration PWR- PWR- I I O O I I
Pin Name VCC GND IRIN ADC[5:0] PWM9 PWM[8:1] Port0[F:0] Port1[9:0] SCLb SCDc XTAL1 XTAL2 LPF HSYNC VSYNC /RESET V[3:1] Blank Half Blankd RGB Digital Outputse SCLKf
Function +5V 0V Infrared Remote Capture Input 4-Bit Analog to Digital Converter Input 14-Bit Pulse Width Modulator Output 8-Bit Pulse Width Modulator Output Bit Programmable Input/Output Ports Bit Programmable Input/Output Ports I2C Clock I/O I2C Data I/O Crystal Oscillator Input Crystam Oscillator Output Loop Filter H_Sync V_Sync Device Reset OSD Video Output (Typically Drive B, G, and R Outputs) OSD Blank Output OSD Half Blank Output R[1:0],G[1:0], and B[1:0] Outputs of the RGB Matrix Internal Processor SCLK
40-Pin, Z89302/04/06 29,- 31,- 2 -,9,8,4,27,34 1 -,-,40,39,38 -,-,-,-,-,-,13,12,11,10,9,8,7,6,5,4 -,3,27,20,19,18,17,16,15,14 5 or 15 6 or 16 30 32 33 21 22 28 23,24,25 26 - 19,18,17,14,12,3
Direction
I nAI OD/Oa OD/Oa B B BOD BOD AI AO AB B B I O O O O O
I O O I I I O O I
Notes: a) Port19 is not available on the 40-pin DIP Version, Revision D is Push-Pull. b) SCL I/O pin is shared with Port01 or Port11 c) SCD I/O pin is shared with Port02 or Port12 d) Half Blank output is a function shared with Port0F. Half Blank output is not available on the 40-pin DIP version. e) Digital RGB outputs and the internal SCLK are shared with Port1[5:0]. f) Internal processor SCLK is shared with Port16.
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PRELIMINARY
Z89302/04/06 Digital Television Controller
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VID VIA VO VO IOH IOH IOL IOL TA TA Parameter Power Supply Voltage Input Voltage Input Voltage Output Voltage Output Voltage Output Current High Output Current High Output Current Low Output Current Low Operating Temperature Storage Temperature Min 0 -0.3 -0.3 -0.3 -0.3 Max 7 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 -10 -100 20 200 70 150 Units V V V V V mA mA mA mA C C Digital Inputs Analog Inputs (A/D0-A/D4) All Push-Pull Digital Output Open-Drain/Push-Pull PWM Outputs (PWM1-PWM8) One Pin All Pins One Pin All Pins Conditions
1
0 -65
Note: Revision D and later have push-pull PWM outputs.
DC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to + 5.5 V; FOSC = 32.768 kHz
Symbol VIL VIH VPU VOL VOL VXL VXH VHY IIR IIL ICC ICC1E ICC1 ICC2 IADC IADC Parameter Input Voltage Low Input Voltage High Max. Pull-Up Voltage Output Voltage Low Output Voltage High Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current Input Leakage Supply Current Supply Current of the OTP Supply Current Supply Current Input Current Input Current VCC-0.9 0.3 VCC VCC-2.0 3.0 -3.0 0.75 150 3.0 100 700 300 10 0.5 10 Min 0 0.6 VCC Max 0.2 VCC VCC 5 0.4 0.16 4.75 1.0 3.5 0.5 90 0.01 60 300 100 5 Typical 0.4 3.6 Units V V V V V V V V mA mA mA mA mA mA mA mA All Pins @ IOL = 1 mA @ IOL = 0.75 mA External Clock Generator Driven On XTAL1 Input Pin VRL = 0V @ 0 V and VCC Sleep Mode @ 32 kHz Sleep Mode @ 32 kHz Sleep Mode C Revision D Revision Conditions
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Z89302/04/06 Digital Television Controller
PRELIMINARY
V1,V2,V3 ANALOG OUTPUT
Condition 11 10 01 00 4.75 V 3.6 - 4.4 5.25 V 4.0 - 5.0 VII
79% of VII 5% 50% of VII 5% 0.0 - 0.8V
Notes: Maximum Variance Between V1, V2, V3 is 100 mV Settling Time 70% of DC Level, 10pF Load <50n Sec
47 pF 32.768K 10 MOhm
XTAL1
XTAL2 68 pF 27 K
32K Oscillator Recomended Circuit
Figure 3. 32K Oscillator Recommended Circuit
Z893XX
510 W 10 mF
0.1 mF
Figure 4. Low Pass Filter
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PRELIMINARY
Z89302/04/06 Digital Television Controller
AC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 kHz
Symbol TPC TRC,TFC TDPOR Parameter Input Clock Period Clock Input Rise and Fall Power-On Reset Delay 0.8 Min 16 Max 100 Typical 32 12 1.2 Units ms ms s
1
AC CHARACTERISTICS TA = 0C to + 70C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 kHz
Symbol TWRES TDHS TDVS TDES TDOS TWHVS Parameter Power-On Reset Min. Width H_Sync Incoming Signal Width V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync on Even Field Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width
2
Min. 5.5 0.15 -12 20
Max. 5TPC 12.5 1.5 +12 44 2.0
2
Typical 11 1.0 0 32 0.5
Units ms ms ms ms ms ms
Note: All timing of the I C bus interface is defined by related specifications of the I C bus interface.
ANALOG INPUT
ADC0 Step 1 15 Min. 1.45 Step 1 + 0.468 Max 1.55 Step 1 + 0.532 ADC1 Step 1 15
Note: VCC = 5V
Min. 0.2 Step_1 + 4.95
Max 0.4 Step_1 + 5.15
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Z89302/04/06 Digital Television Controller
PRELIMINARY
Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems
and delays. No production release is authorized or committed until the Customer and Zilog have agreed upon a Customer Procurement Specification for this project.
Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or nonconformance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues.
(c) 1996 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc., 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX: (408) 370-8056 Internet: http://www.zilog.com
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