| PART |
Description |
Maker |
| CY7C1141V18 CY7C1145V18 CY7C1156V18 CY7C1143V18 CY |
18-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 2M X 9 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor Corp.
|
| CY7C1263V18-300BZI |
36-Mbit QDRII SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 2M X 18 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1268XV18-600BZXC CY7C1270XV18-600BZXC CY7C1268 |
36-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor
|
| CY7C1263KV18-400BZC CY7C1265KV18-550BZC |
36-Mbit QDRII SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress
|
| CY7C1243KV18-400BZC CY7C1243KV18-450BZC CY7C1245KV |
36-Mbit QDRII SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
|
Cypress
|
| CY7C2163KV18-450BZXI CY7C2163KV18-550BZXI CY7C2165 |
18-Mbit QDRII SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
|
Cypress
|
| CY7C1241V18 CY7C1243V18 CY7C1241V18-300BZC CY7C124 |
36-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的国防评估报告⑩- II SRAM4字突发架构（2.0周期读写延迟
|
Cypress Semiconductor Corp.
|
| M48Z2M1Y10 M48Z2M1V-85PL1 M48Z2M1Y-85PL1 M48Z2M1Y- |
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER庐 SRAM
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER? SRAM
2M X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP36
|
STMicroelectronics
|
| CY7C1471V25-100AXC CY7C1473V25-100AXI CY7C1473V25- |
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBLArchitecture 4M X 18 ZBT SRAM, 8.5 ns, PQFP100
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBLArchitecture 4M X 18 ZBT SRAM, 6.5 ns, PBGA165
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
|
Cypress Semiconductor, Corp.
|
| CAT64LC20ZS CAT64LC20ZP CAT64LC20J-TE7 CAT64LC20J- |
36-Mbit QDR™-II SRAM 4-Word Burst Architecture
36-Mbit QDR™-II SRAM 2-Word Burst Architecture
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture
4-Mbit (128K x 36) Flow-through SRAM with NoBL™ Architecture
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture
SPI Serial EEPROM SPI串行EEPROM
36-Mbit QDR™-II SRAM 2-Word Burst Architecture SPI串行EEPROM
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM SPI串行EEPROM
256K (32K x 8) Static RAM SPI串行EEPROM
|
Analog Devices, Inc.
Electronic Theatre Controls, Inc.
|
