| PART |
Description |
Maker |
| SMT05E SMT05E-05S1V5J SMT05E-05W3V3J |
0.75 Vin to 3.63 Vin Single output
|
Artesyn Technologies
|
| MIC69151 MIC69151-1.8YML MIC69153YME MIC69153YML M |
Single Supply VIN, Low VIN, Low VOUT, 1.5A LDO
|
Micrel Semiconductor
|
| MIC69101 MIC69101-1.8YML MIC69103YML |
Single Supply VIN, LOW VIN, LOW VOUT, 1A LDO
|
Micrel Semiconductor
|
| 5962-8876904KYA 5962-8876904KYC 5962-8876904KPA 59 |
5962-8876801PC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876904KPA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876904KXA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876904KPC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-88769022A · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876903FC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901PC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901PA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901XA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901YA · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
5962-8876901YC · Hermetically Sealed Low If Wide Vcc Logic Gate Optocouplers
|
Agilent (Hewlett-Packard)
|
| LTM4611 |
Ultralow VIN, 15A DC/DC 楼矛Module Regulator
Ultralow VIN, 15A DC/DC μModule Regulator
|
Linear Technology
|
| MAX6754UKLD0-T MAX6755UKLD0-T MAX6756UKLD0-T MAX67 |
Vcc: 5.0 V, active timeout period: 0.02 ms, low-power single/dual-voltage window detector
Vcc: 3.0 V, active timeout period:0.02 ms, low-power single/dual-voltage window detector
Vcc: 5.0 V, active timeout period: 100 ms-320 ms, low-power, single/dual-voltage window detector
Vcc: 5.0 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 2.5 V, Vcc:1.8 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 3.3 V, Vcc: 1.8 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 3.3 V, active timeout period:0.02 ms, low-power single/dual-voltage window detector
Vcc: 3.3 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 1.8 V, active timeout period:0.02 ms, low-power single/dual-voltage window detector
Vcc: 3.0 V, active timeout period:185 ms, low-power single/dual-voltage window detector
Vcc: 1.8 V, Vcc:adj, active timeout period:185 ms, low-power single/dual-voltage window detector
|
MAXIM - Dallas Semiconductor
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| MIC2561 MIC2561-0BM MIC2561-1BM |
PCMCIA Card Socket VCC & VPP Switching Matrix
PCMCIA Card Socket VCC & VPP Switching Matrix 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14
|
MICREL[Micrel Semiconductor]
Micrel Semiconductor,Inc.
Micrel Semiconductor, Inc.
|
| KM416C1004CJ-5 KM416C1004CJ-6 KM416C1004CJL-6 KM41 |
1M x 16Bit CMOS dynamic RAM with extended data out, 50ns, VCC=5.0V, refresh period=64ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, refresh period=64ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, self-refresh
1M x 16Bit CMOS dynamic RAM with extended data out, 50ns, VCC=5.0V, refresh period=16ms
1M x 16Bit CMOS dynamic RAM with extended data out, 60ns, VCC=5.0V, refresh period=16ms
1M x 16Bit CMOS dynamic RAM with extended data out, 45ns, VCC=5.0V, self-refresh
|
Samsung Electronic
|
| LP28052A-01 |
Vin Over Voltage Protection:6.5V
|
Lowpower Semiconductor ...
|
| PMO-4530PN-47UQ |
Sensitivity Range -47 ± 3 dB RL = 2.2 k Vcc = 2.0v
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Mallory performance clu...
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