| PART |
Description |
Maker |
| DDU12H-75C3 DDU12H-750MC3 DDU12H-XXC3 DDU12H-XXM D |
5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) ACTIVE DELAY LINE, TRUE OUTPUT, DSO24
5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) ACTIVE DELAY LINE, TRUE OUTPUT, DIP17
5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) 5，技术咨询，经过ECL接口固定延迟线（系列DDU12H
|
Data Delay Devices, Inc.
DATA DELAY DEVICES INC
|
| DDU12H-XXMC3 DDU12H DDU12H-1000C3 DDU12H-1000M DDU |
5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H)
|
DATADELAY[Data Delay Devices, Inc.]
|
| MDU14-9MC4 MDU14 MDU14-10 MDU14-10C4 MDU14-10M MDU |
QUAD, ECL-INTERFACED FIXED DELAY LINE (SERIES MDU14)
|
DATADELAY[Data Delay Devices, Inc.]
|
| MDU14-5C4 MDU14-7C4 |
QUAD, ECL-INTERFACED FIXED DELAY LINE (SERIES MDU14) 四，经过ECL接口固定延迟线（系列MDU14
|
Data Delay Devices, Inc.
|
| MDU3C-100M |
Delay 100 /-5 ns, triple, HCMOS-interfaced fixed delay line
|
Data Delay Devices Inc
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| SY100EL90V SY100EL90VZC SY100EL90VZCTR SY100EL90VZ |
TRIPLE ECL TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO20
5V/3.3V TRIPLE ECL/LVECL-TOPECL/LVPECL TRANSLATOR
|
MICREL INC
Micrel Semiconductor
|
| PDU10256HSERIES PDU10256H-0.5C5 |
8-BIT, ECL-interfaced programmable delay line
8-BIT. ECL-INTERFACED PROGRAMMABLE DELAY LINE
|
Data Delay Devices Inc
|
| AND8090 AND8090D MC100H601 MC100H601FN MC10H106FN |
3.3V / 5V ECL Quad 2-Input Differential AND/NAND
5V ECL Low Impedance Driver
LOW VOLTAGE DUAL 1:4, 1:5 DIFFERENTIAL FANOUT BUFFER
8 Input Priority Encoder
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock
3.3V Dual Differential LVPECL to LVTTL Translator
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL 1:15 Differential ÷1/÷2 Clock Driver
Fibre Channel Coaxial Cable Driver and Loop Resillency Circuit
3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS
3.3V / 5V Programmable PLL Synthesized Clock Generator (25 to 400 MHz)
2.5 V/3.3 V SiGe 1:2 Differential Clock Driver with RSECL Outputs
2.5 V/3.3 V SiGe 1:10 Differential Clock Driver with RSECL Outputs
Triple 4-3-3-Input NOR Gate
9-Bit ECL-TTL Translator
AC Characteristics of ECL Devices
|
Motorola
ONSEMI[ON Semiconductor]
|
| SY100EL91ZCTR SY100EL91L SY100EL91ZC SY100EL91ZG S |
TRIPLE PECL-TO-ECL TRANSLATOR
3.3V TRIPLE LVPECL-to-ECL OR LVPECL-to-LVECL TRANSLATOR
|
Micrel Semiconductor
|
